features access times of 150, 200, 250 and 350ns single 5v10% power supply fast byte write (200s or 1 ms) low power cmos: - 60 ma active current - 150 a standby current fast write cycle time rdy/ busy pin is not connected for the pya28c64x cmos & ttl compatible inputs and outputs endurance: - 10,000 write cycles - 100,000 write cycles (optional) data retention: 10 years available in the following package: C 28-pin 600 mil ceramic dip C 32-pin ceramic lcc (450x550 mils) functional block diagram pin configurations dip (c5-1) description the pya28c64 is a 5 volt 8kx8 eeprom. the pya28c64 features data and rdy/ busy (pya28c64 only) to indicate early completion of a write cycle. data retention is 10 years. the device is available in a 28-pin 600 mil wide ceramic dip and 32-pin lcc. lcc (l6) note: the rdy/ busy pin is not connected for the pya28c64x. document # eeprom105 rev b revised june 2012 pya28c64(x) 8k x 8 eeprom
page 2 grade (2) ambient temp gnd v cc military -55c to +125c 0v 5.0v 10% operation read read operations are initiated by both oe and ce low. the read operation is terminated by either ce or oe re - turning high. this two line control architecture elimi - nates bus contention in a system environment. the data bus will be in a high impedance state when either oe or ce is high. byte write write operations are initiated when both ce and we are low and oe is high. the pya28c64 supports both a ce and we controlled write cycle. that is, the address is latched by the falling edge of either ce or we , whichever occurs last. similarly, the data is latched internally by the rising edge of either ce or we , whichever occurs frst. a byte write operation, once initiated, will automatically con - tinue to completion. chip clear the contents of the entire memory of the pya28c64 may be set to the high state by the chip clear operation. by setting ce low and oe to 12 volts, the chip is cleared when a 10 msec low pulse is applied to we . device identification an extra 32 bytes of eeprom memory are available to the user for device identifcation. by raising a 9 to 12 0.5v and using address locations 1fe0h to 1fffh the additional bytes may be written to or read from in the same manner as the regular memory array. data polling the pya28c64 features data polling as a method to in - dicate to the host system that the byte write cycle has completed. data polling allows a simple bit test opera - tion to determine the status of the pya28c64, eliminat - ing additional interrupts or external hardware. during the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on i/o 7 (i.e., write data=0xxx xxxx, read data=1xxx xxxx). once the programming cycle is complete, i/o 7 will refect true data. ready/ busy pin 1 is an open drain rdy/ busy output that can be used to detect the end of a write cycle. rdy/ busy is actively pulled low during the write cycle and is released at the completion of the write. the open drain connec - tion allows for or-tying of several devices to the same rdy/ busy line. the rdy/ busy pin is not connected for the pya28c64x. sym parameter value unit v cc power supply pin with respect to gnd -0.3 to +6.25 v v term terminal voltage with respect to gnd (up to 6.25v) -0.5 to +6.25 v t a operating temperature -55 to +125 c t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma maximum ratings (1) recommended operating conditions capacitances (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions typ unit c in input capacitance v in = 0v 10 pf c out output capacitance v out = 0v 10 pf pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 3 dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter test conditions pya28c64 unit min max v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage -0.5 (3) 0.8 v v hc cmos input high voltage v cc - 0.2 v cc + 0.5 v v lc cmos input low voltage -0.5 (3) 0.2 v v ol output low voltage (ttl load) i ol = +2.1 ma, v cc = min 0.45 v v oh output high voltage (ttl load) i oh = -0.4 ma, v cc = min 2.4 v i li input leakage current v cc = max v in = gnd to v cc -10 +10 a i lo output leakage current v cc = max, ce = v ih , v out = gnd to v cc -10 +10 a i sb standby power supply current (ttl input levels) ce v ih , oe = v il , v cc = max, f = max, outputs open 5 ma i sb1 standby power supply current (cmos input levels) ce v hc , v cc = max, f = 0, outputs open, v in v lc or v in v hc 150 a i cc supply current ce = oe = v il , we = v ih , all i/o's = open, inputs = v cc = 5.5v 60 ma notes: 1. stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than -3.0v and -100ma, respectively, are permissible for pulse widths up to 20ns. 4. this parameter is sampled and not 100% tested. pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 4 sym parameter -150 -200 -250 -350 unit min max min max min max min max t avav read cycle time 150 200 250 350 ns t avqv address access time 150 200 250 350 ns t elqv chip enable access time 150 200 250 350 ns t olqv output enable access time 80 100 100 100 ns t elqx chip enable to output in low z 0 0 0 0 ns t ehqz chip disable to to output in high z 55 60 65 70 ns t olqx output enable to output in low z 0 0 0 0 ns t ohqz output disable to output in high z 55 60 65 70 ns t avqx output hold from address change 0 0 0 0 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2) timing waveform of read cycle pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 5 ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) symbol parameter 150 / 200 / 250 / 350 unit min max t elrh t wlrh write cycle time 1 ms t avel t avwl address setup time 10 ns t elax t wlax address hold time 50 ns t wlel write setup time 0 ns t wheh write hold time 0 ns t ohel t ohwl oe setup time 10 ns t whol t ehol2 oe hold time 10 ns t eleh t wlwh we pulse width 100 1000 ns t dveh t dvwh data setup time 50 ns t ehdx t whdx data hold time 10 ns t elwl ce setup time 0 ns t ehwh ce hold time 0 ns t ehrl t whrl time to device busy 50 ns pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 6 timing waveform of byte write cycle ( ce controlled) timing waveform of byte write cycle ( we controlled) pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 7 ac test conditions truth table input pulse levels gnd to 3.0v input rise and fall times 10ns input timing reference level 1.5v output timing reference level 1.5v output load see figure 1 mode ce oe we i/o read l l h d out write l h l d in write inhibit x l x write inhibit x x h standby h x x high z output disable x h x high z figure 1. output load pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 8 ordering information pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 9 side brazed dual in-line package (600 mils) pkg # l6 # pins 32 symbol min max a 0.060 0.075 a1 0.050 0.065 b1 0.022 0.028 d 0.442 0.458 d1 0.300 bsc d2 0.150 bsc d3 - 0.458 e 0.540 0.560 e1 0.400 bsc e2 0.200 bsc e3 - 0.558 e 0.050 bsc h 0.040 ref j 0.020 ref l 0.045 0.055 l1 0.045 0.055 l2 0.075 0.095 nd 7 ne 9 rectangular leadless chip carrier pkg # c5-1 # pins 28 (600 mil) symbol min max a - 0.232 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.490 e 0.500 0.610 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.060 s1 0.005 - s2 0.005 - pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
page 10 revisions document number eeprom105 document title pya28c64(x) - 8k x 8 eeprom rev issue date originator description of change or jul 2010 jdb new data sheet a nov 2011 jdb updated ordering info b jun 2012 jdb updated ordering info; changed "simple byte write" to " fast byte write (200s or 1 ms)" on p.1 pya28c64 - 8k x 8 eeprom document # eeprom105 rev b
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